The present invention relates to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET) device for a dynamic random access memory (DRAM) cell, and more particularly, to a method for forming a P-type halo implant surrounding the N+ bitline diffusion region of such device.
Over the last several years, significant advances have occurred in increasing the circuit density in integrated circuit chip technology. The ability to provide significantly increased numbers of devices and circuits on an integrated circuit chip has, in turn, created an increased desire to incorporate or integrate additional system functions onto a single integrated circuit chip. In particular, an increasing need exists for joining both memory circuits and logic circuits together on the same integrated circuit chip.
As minimum feature size and cell architecture (i.e. number of squares) are scaled down, robust design points for DRAM cells utilizing planar MOSFETs and deep storage capacitors are increasingly difficult to achieve. Scalability of the planar MOSFET in this environment is severely limited by reliability imposed constraints on minimum gate insulator thickness and poor scalability of physical attributes such as buried strap outdiffusion, active area (AA) and gate conductor (GC) critical dimension, GC-deep trench (DT) overlay tolerance, and shallow trench isolation (STI) recess control. One manifestation of the scalability difficulties of planar DRAM MOSFETs is degradation of the retention time tail, due to increased junction leakage resulting from the very high channel doping concentrations, which are required to suppress short-channel effects.
Another problem associated with scaling the design channel length of the array MOSFET is large threshold voltage (V.sub.t) variation due to operation on the steep portion of the V.sub.t rolloff curve. Due to variations in GC critical dimension (CD) and GC-DT overlay, the drain induced barrier effect (DIBL) from the proximity of the bitline diffusion to buried strap diffusion result in a variation of threshold voltage. With aggressively scaled channel lengths, operation on the steep portion of the rolloff curve occurs since the gate oxide thickness and the strap junction depth of the array MOSFET are very difficult to scale. As a result of amplified variation in threshold voltage the amount of charge that can be written to the storage capacitor is reduced. This reduction in stored charge results in decreased product yield.
To meet the performance objectives in contemporary DRAMs it is necessary to provide support MOSFETs having source-drain diffusions, which are contacted with low-resistance (tungsten) studs. Because of the relatively low doping concentration required for the storage node diffusion in the array (to contain junction leakage) and a process which simultaneously forms the bitline diffusion and node diffusion, metal studs cannot be used for the array MOSFET; doped polysilicon studs are customarily used. If tungsten studs were also used for contacting the array MOSFETs, very high junction leakage would result because of tungsten penetration into the junction.
Thus, there is no current effective, economically attractive process for providing a MOSFET with improved threshold voltage (V.sub.t) control without increased node diffusion leakage.